1. The Field of the Invention
The present invention relates generally to micro-structure manufacturing technology. More specifically, the present invention relates to a method and mechanism for manufacturing a pre-metal dielectric layer that is resistant to soft errors and defects.
2. Background and Relevant Art
Manufactured micro-structures are playing an ever more important role in the advancement of civilization. Such micro-structures may include, for example, semiconductor circuits, which are present in almost every device or system that implements some form of electronic logic or function. Micro-structures may also include Micro-Electro-Mechanical Systems (MEMS) devices. Such MEMS devices may include, for example, microscopic devices that accomplish some function using electrical and mechanical principles. General examples of conventional MEMS devices include micro-sensors, micro-motors, micro-gears, or the like. MEMS devices may be manufactured using semiconductor material or non-semiconductor materials.
In recent generations, feature dimension sizes have become smaller and smaller, both for semiconductor circuits and MEMS. Furthermore, the number of metallization layers in a typical semiconductor circuit has increased in order to provide as much circuitry per unit area of die space. In order to selectively isolate the various metallization layers, a dielectric material is typically formed between the metallization layers, with conductive vias formed at the points where connections are desired. In addition, proper selective isolation from the underlying substrate (e.g., a semiconductor wafer) is achieved by fabricating a pre-metallization dielectric layer over the wafer prior to fabricating any metallization layers. Once again, appropriate conductive vias are formed to provide appropriate electrical connections with the underlying substrate.
In order to promote structural integrity and thus reduced defects in the fabricated micro-structure, it is important that each layer be manufactured upon a smooth and flat surface. Accordingly, after manufacturing each dielectric layer (both the pre-metallization dielectric layer and any inter-metallization dielectric layers) it is important to planarize the surface of the dielectric layer prior to forming other structures on top of that surface.
Chemical Mechanical Polishing (CMP) technology combines chemical and mechanical effects to polish the surface of a dielectric layer to be relatively smooth. However, even with such CMP technology, scratching of the dielectric layer surface may occur, thereby introducing non-flat features onto the top surface of the dielectric layer. Such scratches may significantly increase the defects in the finished micro-structure.
One cause of scratching is from the intrinsic stress of the dielectric material. If the dielectric material has intrinsic tensile stress, the dielectric surface will have some concavity, with the level of concavity being dependent on the magnitude of the tensile stress. Similarly, if the dielectric material has intrinsic compressive stress, the dielectric surface will have some convexity, with the level of convexity being dependent on the magnitude of the compressive stress. Such concavity or convexity in the top surface of the dielectric layer means that the more elevated portions of the top surface are more roughly engaged with the CMP polishing pad than other portions of the top surface. This causes the elevated portions to be more susceptible to scratching.
Some dielectric materials use dopants such as boron in order to reduce the flow temperature of the dielectric material. Thus, lower temperatures may be applied to the wafer and allow gravity to flatten the top surface of the dielectric material, to thereby avoid the CMP process. It is desirable to lower the flow temperature since higher temperatures can cause unwanted diffusion to occur thereby changing the electrical or mechanical characteristics of the micro-structure.
However, the use of boron dopants presents some reliability problems, especially for electronic circuitry. Specifically, boron easily decays. When boron10 atoms are struck by photons having certain energy levels, the boron nucleus splits releasing a Lithium nucleus, an alpha particle, and a neutron. The occurrence of these particles can affect the electrical characteristics of any surrounding circuitry. Errors caused by this decay are called “soft errors”. Boron dopant decay has been shown to be a source of soft errors in a variety of memories and logic circuitry.
Another important property of a dielectric material is that it be uniformly dense. This is because via holes are often etched through the dielectric material in order to later form conductive vias needed for electrical connections between metallization layers, or with the underlying substrate. However, the etch rate of the dielectric material is a strong function of the density of the material. Accordingly, uniform density of the dielectric material means that the via holes are relatively uniformly etched. This uniform density thereby reduces defects due to incomplete via holes causing an undesigned open circuit.
One conventional technology that achieves highly uniform density involves the use of BoroPhosphoSilicate Glass (BPSG) as the pre-metallization dielectric layer. With the application of heat in the range of from 800 degrees Celsius to 1000 degrees Celsius, the BPSG glass will flow to fill in gaps in the underlying structure with uniform density. Such temperatures do not cause significant adverse diffusion that could degrade the function of the structure. However, the use of BPSG glass has at least two disadvantages.
First, although the density is uniform, its density is also low, which makes the material susceptible to scratching. For example, FIG. 3 shows a cross sectional view of a BPSG pre-metallization dielectric layer with several fractures induced by scratches in its top surface. These scratches may also cause electrical failure. For example, FIG. 4 shows a top view of a BPSG pre-metallization dielectric layer with several dispersed tungsten vias. Between two of the vias, an arching micro-scratch has been inadvertently filled with tungsten, thereby causing an undesigned short between two of the vias. The reduction of scratching would improve the yield in fabrication of the micro-structure.
Second, the presence of the boron material in the BPSG dielectric material may cause the soft errors mentioned above, thereby adversely affecting the electrical performance of any surrounding circuitry.
More recently, High Density Plasma (HDP) Chemical Vapor Deposition (CVD) has been used to form the pre-metallization dielectric layer. This technology allows for the deposition of a dielectric material that fills gaps in the underlying structure, without applying heat, and without the use of dopants. Furthermore, the resulting dielectric material has increased film density, thereby improving its resistance to scratching. However, capital equipment needed to perform HDP CVD processes is expensive. Furthermore, this technology is relatively new, which translates to higher defectivity due the lack of technological maturity. In addition, the use of HDP as the deposition mechanism in active areas may cause plasma-induced damage to the surrounding structure.
Accordingly, what would be advantageous are methods and mechanisms for forming a pre-metallization layer of high density and lower stress, with reduced soft errors, at temperatures that would not cause significant adverse diffusion, and that do not rely on expensive and potentially damaging HDP CVD processes.